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TrilithICTM
BTS 771 G
Overview Features * * * * Quad switch driver Free configurable as bridge or quad-switch Optimized for DC motor management applications Ultra low RDS ON @ 25 C: High-side switch: typ. 85 m, P-DSO-28-9 Low-side switch: typ. 40 m Very high peak current capability Very low quiescent current Space- and thermal optimized power P-DSO-Package Load and GND-short-circuit-protected Operates up to 40 V Status flag diagnosis Overtemperature shut down with hysteresis Short-circuit detection and diagnosis Open-load detection and diagnosis C-MOS compatible inputs Internal clamp diodes Isolated sources for external current sensing Over- and under-voltage detection with hysteresis Ordering Code Q67007-A9274 Package P-DSO-28-9
* * * * * * * * * * * * *
Type BTS 771 G Description
The BTS 771 G is a TrilithIC contains one double high-side switch and two low-side switches in one P-DSO-28-9 -Package. "Silicon instead of heatsink" becomes true The ultra low RDS ON of this device avoids powerdissipation. It saves costs in mechanical construction and mounting and increases the efficiency. The high-side switches are produced in the SIEMENS SMART SIPMOS(R) technology. It is fully protected and contains the signal conditioning circuitry for diagnosis. (The comparable standard high-side product is the BTS 621L1.)
Semiconductor Group 1 1999-01-07
BTS 771 G
For minimized RDS ON the two low-side switches are produced in the SIEMENS Millifet logic level technology (The comparable standard product is the BUZ 103AL). Each drain of these three chips is mounted on separated leadframes (see P-DSO-28-9 pin configuration). The sources of all four power transistors are connected to separate pins. So the BTS 771 G can be used in H-Bridge configuration as well as in any other switch configuration. Moreover, it is possible to add current sense resistors. All these features open a broad range of automotive and industrial applications.
Semiconductor Group
2
1999-01-07
BTS 771 G
DL1 GL1 DL1 N.C. DHVS GND GH1 ST GH2
1 2 3 4 5 6 7 HS-Lead Frame 8 9 LS-Lead Frame 1
28 DL1 27 SL1 26 SL1 25 DL1 24 DHVS 23 SH1 22 SH1 21 SH2 20 SH2 19 DHVS 18 DL2 LS-Lead Frame 2 17 SL2
DHVS 10 N.C. DL2 GL2 DL2 11 12 13 14
16 SL2 15 DL2
AEP02071
Figure 1
Pin Configuration (top view)
Semiconductor Group
3
1999-01-07
BTS 771 G
Pin Definitions and Functions Pin No. 1, 3, 25, 28 2 4 5, 10, 19, 24 6 7 8 9 11 12, 14, 15, 18 13 16, 17 20, 21 22, 23 26, 27
1)
Symbol DL1 GL1 N.C. DHVS GND GH1 ST GH2 N.C. DL2 GL2 SL2 SH2 SH1 SL1
Function Drain of low-side switch1 Leadframe 1 1) Gate of low-side switch1 not connected Drain of high-side switches and power supply voltage Leadframe 2 1) Ground Gate of high-side switch1 Status of high-side switches; open Drain output Gate of high-side switch2 not connected Drain of low-side switch2 Leadframe 3 1) Gate of low-side switch2 Source of low-side switch2 Source of high-side switch2 Source of high-side switch1 Source of low-side switch1
To reduce the thermal resistance these pins are direct connected via metal bridges to the leadframe.
Bold type: Pin needs power wiring
Semiconductor Group
4
1999-01-07
BTS 771 G
DHVS 5, 10, 19, 24 ST 8 DST C6V1 Diagnosis Biasing and Protection
GH1
7
R I1
3.5 k
GH2
9
R I2
3.5 k
GND
6
Driver IN OUT 1212 DI1 C6V1 0 0 L L 01LH 10HL 11HH DI2 C6V1
R O1
10 k
R O2
10 k
20, 21
SH2
12, 14, 15, 18 22, 23 1, 3, 25, 28
DL2 SH1 DL1
GL1
2
GL2
13 26, 27 SL1 16, 17 SL2
AEB02072
Figure 2
Block Diagram
Semiconductor Group
5
1999-01-07
BTS 771 G
Circuit Description Input Circuit The control inputs GH1,2 consist of TTL/CMOS compatible Schmitt-Triggers with hysteresis. Buffer amplifiers are driven by these stages and convert the logic signal into the necessary form for driving the power output stages. The inputs GH1 and GH2 are connected to a standard N-channel logic level power-MOS gate. Output Stages The output stages consist of an ultra low RDS ON Power-MOS H-Bridge. Protective circuits make the outputs short circuit proof to ground and load short circuit proof. Positive and negative voltage spikes, which occur when driving inductive loads, are limited by integrated power clamp diodes. Short Circuit Protection (valid only for the high-side switches) The outputs are protected against - output short circuit to ground, and - overload (load short circuit). An internal OP-Amp controls the Drain-Source-Voltage of the HS-Switches by comparing the DS-Voltage-Drop with an internal reference voltage. Above this trippoint the OP-Amp reduces the output current depending on the junction temperature and the drop voltage. In the case of overloaded high-side switches the status output is set to low. If the HS-Switches are in OFF-state-Condition internal resistors RO1,2 from SH1,2 to GND pull the voltage at SH1,2 to low values. On each output pin SH1 and SH2 an output examiner circuit compares the output voltages with the internal reference voltage VEO. This results in switching the status output to low. In H-Bridge condition this feature can be used to protect the low-side switches against short circuit during the OFF-period. Overtemperature Protection (valid only for the high-side-switches) The chip also incorporates an overtemperature protection circuit with hysteresis which switches off the output transistors and sets the status output to low. Undervoltage-Lockout (UVLO) When VS reaches the switch-on voltage VUVON the IC becomes active with a hysteresis. The High-Side output transistors are switched off if the supply voltage VS drops below the switch off value VUVOFF.
Semiconductor Group
6
1999-01-07
BTS 771 G
Overvoltage-Lockout (OVLO) When VS reaches the switch-off voltage VOVOFF the High-Side output transistors are switched off with a hysteresis. The IC becomes active if the supply voltage VS drops below the switch-on value VOVON. Open Load Detection Open load is detected by current measurement. If the output current drops below an internal fixed level the error flag is set with a delay. Status Flag Various errors as listed in the table "Diagnosis" are detected by switching the open drain output ST to low.
Semiconductor Group
7
1999-01-07
BTS 771 G
Truthtable and Diagnosis (valid only for the High-Side-Switches) Flag GH1
0 0 1 1 0 0 1 0 1 X 0 0 1 0 1 X 0 1 X X 0 X 1 X
GH2
0 1 0 1 0 1 X 0 0 1 0 1 X 0 0 1 X X 0 1 0 1 X X
SH1
L L H H Z Z H L H X H H H L H X L L X X L L L L
SH2
L H L H L H X Z Z H L H X H H H X X L L L L L L
ST Remarks
1 1 1 1 1 1 0 1 1 0 0 1 1 0 1 1 1 0 1 0 1 0 0 1 stand-by mode switch2 active switch1 active both switches active
Inputs
Normal operation; identical with functional truth table
Outputs
Open load at high-side switch1
detected
Open load at high-side switch2
detected detected
Short circuit to DHVS at high-side switch1
Short circuit to DHVS at high-side switch2
detected
Overtemperature high-side switch1 Overtemperature high-side switch2 Overtemperature both high-side switch
detected detected detected detected not detected
Over- and Under-Voltage
Inputs: 0 = Logic LOW 1 = Logic HIGH X = don't care
Outputs: Z = Output in tristate condition L = Output in sink condition H = Output in source condition X = Voltage level undefined
Status: 1 = No error 0 = Error
Semiconductor Group
8
1999-01-07
BTS 771 G
Electrical Characteristics Absolute Maximum Ratings - 40 C < Tj < 150 C Parameter Symbol Limit Values min. max. Unit Remarks
High-Side-Switches (Pins DHVS, GH1,2 and SH1,2) Supply voltage HS-drain current HS-input current HS-input voltage Status Output ST Status Output current
VS IDHS IGH VGH
- 0.3 - 10 -2 - 10
43 * 2 16
V A mA V
- * internally limited Pin GH1 and GH2 Pin GH1 and GH2
IST
-5
5
mA
Pin ST
Low-Side-Switches (Pins DL1,2, GL1,2 and SL1,2) Break-down voltage LS-drain current LS-drain current LS-drain current lS-input voltage Temperatures Junction temperature Storage temperature
V(BR)DSS IDLS IDLS IDLS VGL
50 - - - - 10
- 10 20 30 14
V A A A V
VGS = 0 V; ID <= 1 mA
-
t < 1 ms; < 0.1 t < 0.1 ms; < 0.1
Pin GL1 and GL2
Tj Tstg
- 40 - 50
150 150
C C
- -
Thermal Resistances (one HS-LS-Path active) LS-junction case HS-junction case Junction ambient
RthjCLS RthjCHS Rthja
- - -
20 20 60
K/W measured to pin3 or 12 K/W measured to pin19 K/W -
Note: Maximum ratings are absolute ratings; exceeding any one of these values may cause irreversible damage to the integrated circuit.
Semiconductor Group 9 1999-01-07
BTS 771 G
Operating Range Parameter Supply voltage Input voltages Input voltages Output current HS-junction temperature LS-junction temperature Symbol Limit Values min. max. V V V mA C C After VS rising above VUVON - - - - - Unit Remarks
VS VGH VGL IST TjHS TjLS
VUVOFF 34
- 0.3 -9 0 - 40 - 40 15 13 2 150 150
Note: In the operating range the functions given in the circuit description are fulfilled.
Semiconductor Group
10
1999-01-07
BTS 771 G
Electrical Characteristics
ISH1 = ISH2 = ISL1 = ISL2 = 0 A; - 40 C < Tj < 150 C; 8 V > VS > 18 V
unless otherwise specified Parameter Symbol Limit Values min. Current Consumption Quiescent current typ. max. Unit Test Condition
IS
-
16
30
A
GH1 = GH2 = L
VS = 13.2 V Tj = 25 C
Quiescent current Supply current Supply current
IS IS IS
- - -
- 2 4
35 3.5 7
A mA mA
GH1 = GH2 = L VS = 13.2 V GH1 or GH2 = H GH1 and GH2 = H
Under Voltage Lockout (UVLO) Switch-ON voltage
VUVON Switch-OFF voltage VUVOFF Switch ON/OFF hysteresis VUVHY
Over Voltage Lockout (OVLO)
- 3.5 -
5.4 4.2 1.2
7 - -
V V V
VS increasing VS decreasing VUVON - VUVOFF
VOVOFF Switch-ON voltage VOVON Switch OFF/ON hysteresis VOVHY
Switch-OFF voltage
36 35 -
37.8 37.1 0.7
43 - -
V V V
VS increasing VS decreasing VOVOFF - VOVON
Short Circuit of Highside Switch to GND Initial peak SC current Initial peak SC current Initial peak SC current
ISCP ISCP ISCP
11 9 5
18 14 8
25 22 14
A A A
Tj = - 40 C Tj = 25 C Tj = 150 C
Semiconductor Group
11
1999-01-07
BTS 771 G
Electrical Characteristics (cont'd)
ISH1 = ISH2 = ISL1 = ISL2 = 0 A; - 40 C < Tj < 150 C; 8 V > VS > 18 V
unless otherwise specified Parameter Symbol Limit Values min. Short Circuit of Highside Switch to VS OFF-state examiner-voltage Output pull-down-resistor typ. max. Unit Test Condition
VEO RO
2 4
3 11
4 30
V k
VGH = 0 V
-
Open Circuit Detection of Highside Switch Detection current
IOCD
10
130
400
mA
-
Switching Times of Highside Switch Switch-ON-time; to 90% VSH Switch-OFF-time; to 10% VSH
tON_H tOFF_H
- -
0.2 0.2
0.4 0.4
ms ms
resistive load ISH = 1 A; VS = 12 V resistive load ISH = 1 A; VS = 12 V
Control Inputs of Highside Switches GH 1, 2 H-input voltage L-input voltage Input voltage hysterese H-input current L-input current Input series resistance Zener limit voltage
VGHH VGHL VGHHY IGHH IGHL RI VGHZ
- 1.5 - 20 1 2.5 5.4
2.8 2.3 0.5 60 25 3.5 -
3.5 - - 90 50 6 -
V V V A A k V
- - -
VGH = 5 V VGH = 0.4 V
-
IGH = 1.6 mA
Status Flag Output ST of Highside Switch Low output voltage Leakage current Zener-limit-voltage
Semiconductor Group
VSTL ISTLK VSTZ
- - 5.4
12
0.25 0.5 -
0.6 10 -
V A V
IST = 1.6 mA VST = 5 V IST = 1.6 mA
1999-01-07
BTS 771 G
Electrical Characteristics (cont'd)
ISH1 = ISH2 = ISL1 = ISL2 = 0 A; - 40 C < Tj < 150 C; 8 V > VS > 18 V
unless otherwise specified Parameter Symbol Limit Values min. Control Inputs of Lowside Switches GL1, 2 Gate-threshold-voltage Transconductance typ. max. Unit Test Condition
VGL(th) gfs
0.8 -
1.6 5
2.5 -
V S
VGL = VDSL; IDL = 1 mA VDSL = 20 V; IDL = 20 A
Switching Times of Lowside Switch Switch-ON delay time; VGS = 5 V; RGS = 50 Switch-ON time; VGS = 5 V; RGS = 50 Switch-OFF delay time; VGS = 5 V; RGS = 50 Switch-OFF time; VGS = 5 V; RGS = 50 Thermal Shutdown Thermal shutdown junction TjSD temperature Thermal switch-on junction TjSO temperature Temperature hysteresis T 155 150 - - - 10 190 180 - C C C - - T = TjSD - TjSO
td_ON_L tON_L td_OFF_L tOFF_L
- - - -
25 95 140 85
40 140 190 115
ns ns ns ns
resistive load ISL = 1 A; VS = 12 V resistive load ISL = 1 A; VS = 12 V resistive load ISL = 1 A; VS = 12 V resistive load ISL = 1 A; VS = 12 V
Semiconductor Group
13
1999-01-07
BTS 771 G
Electrical Characteristics (cont'd)
ISH1 = ISH2 = ISL1 = ISL2 = 0 A; - 40 C < Tj < 150 C; 8 V > VS > 18 V
unless otherwise specified Parameter Symbol Limit Values min. Output Stages Leakage current of highside switch Leakage current of lowside switch Clamp-diode of highside switch; Forward-Voltage Clamp-diode leakagecurrent (IFH + ISH) of highside switch Clamp-diode of lowside switch; forward-voltage Static drain-source on-resistance of highside switch Static drain-source on-resistance of lowside switch Static path on-resistance typ. max. Unit Test Condition
IHSLK ILSLK VFH
- - -
5 20 0.8
12 100 1.5
A A V
VGH = VSH = 0 V VGL = 0 V VDS = 18 V IFH = 3 A
ILKCL
-
2
10
mA
IFH = 3 A
VFL
-
0.8
1.5
V
IFL = 3 A
RDS ON H
-
85
110
m
ISH = 1 A Tj = 25 C ISL = 1 A; VGL = 5 V Tj = 25 C RDS ON H + RDS ON L; ISH = 1 A
RDS ON L
-
40
55
m
RDS ON
-
-
300
m
Note: The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specify mean values expected over the production spread. If not otherwise specified, typical characteristics apply at TA = 25 C and the given supply voltage.
Semiconductor Group
14
1999-01-07
BTS 771 G
S FH1, 2 ST , STLK
ST 8 DST C6V1 Diagnosis Driver IN OUT 1212 DI1 C6V1 0 0 L L 01LH 10HL 11HH DI2 C6V1 DHVS 5, 10, 19, 24 Biasing and Protection
CS 470 nF
CL 100 F
+ VS
VDSH2 -VFH2
VDSH1 - VFH1
GH1
VST VSTL VSTZ VGH1 VGH2
GH1 7
R I1
3.5 k
R O1
10 k
R O2
10 k
GH2
GH2 9
R I2
3.5 k
20 SH2 SH2 21
GND 6
12, 14, 15, 18 DL2 DL2 LKL 22, 23 SH1 SH1 1, 3, DL1 DL1 25, 28 LKL
VUVON VUVOFF VOVON VOVOFF
GND LKCL1, 2
GL1 2
VGL1 VGL(th)1
GL2 13
VGL2 VGL(th)2
26, 27 SL1 SL1
16, 17 SL2 SL2
VEO1 VDSL1 - VFL1
VEO2 VDSL2 -VFL2
RDSONH =
VDSH SH
RDSONL =
VDSL SL
AES02079
Figure 3
Test Circuit Named during Open Circuit Named during Leakage-Cond.
HS-Source-Current Named during Short Circuit
ISH1,2
ISCP
IOCD
IHSLK
Semiconductor Group
15
1999-01-07
BTS 771 G
Watchdog Reset Q
TLE 4268G D
I DO1
VS = 12 V CS 22 F
DHVS 5, 10, 19, 24
RQ 100 k
WD R VCC
CQ 22 F
CD 100 nF
GND
RS
10 k
ST 8 DST C6V1 GH1 7 Diagnosis Driver IN OUT 1212 DI1 C6V1 0 0 L L 01LH 10HL 11HH DI2 C6V1
Biasing and Protection
R I1
3.5 k
R O1
10 k
R O2
GH2 9
P
R I2
3.5 k
10 k 12, 14, 15, 18 DL2 22, 23 SH1 1, 3, DL1 25, 28
20 SH2 21 M1
GND 6
GL1 2
GL2 13 26, 27 SL1 16, 17 SL2
AES02074
Figure 4
Application Circuit
Semiconductor Group
16
1999-01-07
BTS 771 G
Package Outlines P-DSO-28-9 (Plastic Dual Small Outline Package)
0.35 x 45
2.65 max
2.45 -0.2
0.2 -0.1
1.27 0.35 +0.15 2) 0.2 28x 28 15 0.1
0.4 +0.8 10.3 0.3
1 Index Marking
18.1 -0.4 1)
14
1) Does not include plastic or metal protrusions of 0.15 max rer side 2) Does not include dambar protrusion of 0.05 max per side
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Semiconductor Group 17
0.23 +0.0 9 8 ma x
GPS05123
7.6 -0.2 1)
Dimensions in mm 1999-01-07

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